Physical Layout Designer
Continium Technologies s.r.o.
Ilkovičova, Karlova Ves, Slovakia, Bratislava (Job with occasional home office)
full-time
From 3 000 EUR/month
Information about the position
Job description, responsibilities and duties
Our team is looking for a colleague who would support our team with the full-custom physical mask design of analogue circuit blocks including parametric-cell (pCell) design, and/or place-and-route (P&R) of digital HDL-based logic circuits. The position includes following tasks:
* Provision of full custom layout tool functionality, including schematic-driven layout connectivity (based on Cadence tool Virtuoso Layout Suite L & XL or Mentor/Tanner or Synopsys)
* Provision of an automated routing solution for full custom and mixed-signal designs (based on Cadence CSR or Synopsys tools)
* Understanding of semiconductor element's matching properties, of parasitic R/L/C elements, and debugging capability to localize the signal disturbance coupling in existing mask layout design.
* Layout verification: design rule check (DRC), electric rule check (ERC), parasitic extraction (RCX) layout vs. Schematic (LVS) using state-of-the art CAD tools (Cadence PVS/Quantus/Pegasus, Mentor Calibre/Galaxy, Synopsys IC compiler)
* Understanding of a chip foundry PDK (process development kit) and its design rules
* Interface to CAD vendors, technology and modelling group
* Quality assurance: component test, test within schematic-to-layout-flow; participation in complete flow quality assurance
* Management of chip TapeOut process (GDSII streamout)
Employee perks, benefits
Working in an international environment in a fast growing company on an absolute leading edge digitizer products using advanced nanometer semiconductor technologies
Requirements for the employee
Candidates with education suit the position
University education (Master's degree)
Postgraduate (Doctorate)
Language skills
Other knowledge
Microsoft Teams - Basic
Simulink (Matlab) - Basic
Programming - Basic
Personality requirements and skills
An ideal candidate posesses following skills and experience:
* Knowledge of RF/mixed-signal design process and CMOS/FinFET semiconductor technologies
* CAD skills required (Cadence, Mentor Graphics/Tanner or Synopsys design environment: physical layout design using Virtuoso or Galaxy, automated P&R using Cadence Space Based Router or Synopsys IC compiler or Mentor Galaxy, and layout verification in Quantus/Pegasus, Calibre)
* Experience in physical mask design and/or design automation for analog / mixed signal IC's
* Experience in programming (Perl, TCL, Shell Scripting, C, C++ skills) would be a benefit
* Analytic work methodology and problem analysis